A differential sampling circuit may include a differential pair of transistors having gates to receive a differential input signal, drains coupled to a clocked current source, and sources coupled to respective nodes of a differential output circuit.
To sample a differential signal twice per clock period, two such sampling circuits may be operated in parallel, using two corresponding clock signals that are 180 degrees out of phase with respect to one another.
Input capacitances of a sampling circuit may impact operation of a system in which the sampling circuit is implemented. Input capacitances may be reduced by reducing the size of input stage transistors. Process variations may, however, lead to significant differences between input-referred offsets of two parallel sampling circuits. Accordingly, at least two corresponding offset compensation systems may be needed to correct for non-correlated offsets.
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